industrial temperature range idt29fct520at/bt/ct multilevel pipeline register 1 august 2000 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ? 2000 integrated device technology, inc. dsc-4215/6 features: ? a, b, and c grades ? low input and output leakage 1a (max.) ? cmos power levels ? true ttl input and output compatibility: ?v oh = 3.3v (typ.) ?v ol = 0.3v (typ.) ? high drive outputs (-15ma i oh , 48ma i ol ) ? meets or exceeds jedec standard 18 specifications ? available in soic, ssop, and qsop packages functional block diagram idt29fct520at/bt/ct multilevel pipeline register description: the 29fct520t contains four 8-bit positive edge-triggered registers. these may be operated as a dual 2-level or as a single 4-level pipeline. a single 8-bit input is provided and any of the four registers is available at the 8-bit, 3-state output. these devices are ideal for high speed burst writes and reads in processor/memory applications. mux octal reg. b1 octal reg. b2 octal reg. a2 octal reg. a1 mux oe y 0 - y 7 8 register control clk i 0 , i 1 1 2 s 0 , s 1 2 d 0 - d 7 8
industrial temperature range 2 idt29fct520at/bt/ct multilevel pipeline register pin configuration register selection s 1 s 0 register 00 b 2 01 b 1 10 a 2 11 a 1 soic/ ssop/ qsop top view 5 6 7 8 9 10 11 12 gnd 1 2 3 4 24 23 22 21 20 19 18 17 vcc 16 15 14 13 s 0 s 1 y 0 y 1 y 2 y 3 y 4 y 5 oe i 0 i 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 clk y 6 y 7 symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +7 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +120 ma absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed vcc by +0.5v unless otherwise noted. 2. inputs and vcc terminals only. 3. output and i/o terminals only. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested. pin description pin names description dx register input port clk clock input. enter data into registers on low-to-high transitions. i 0 , i 1 instruction inputs. see figure 1 and instruction control tables s 0 , s 1 multiplexer select. inputs one of the following registers to be available at the output port: a 1 , a 2 , b 1 , or b 2. oe output enable for 3-state output port y x register output port
industrial temperature range idt29fct520at/bt/ct multilevel pipeline register 3 symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 ? ? v v il input low level guaranteed logic low level ? ? 0.8 v i ih input high current (4) v cc = max. v i = 2.7v ? ? 1a i il input low current (4) v cc = max. v i = 0.5v ? ? 1a i ozh high impedance output current v cc = max. v i = 2.7v ? ? 1a i ozl (3-state output pins) (4) v i = 0.5v ? ? 1 i i input high current (4) v cc = max., v i = v cc (max.) ? ? 1a v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i os short circuit current v cc = max., v o = gnd (3) ?60 ?120 ?225 ma v oh output high voltage v cc = min i oh = ?8ma 2.4 3.3 ? v v in = v ih or v il i oh = ?15ma 2 3 ? v ol output low voltage v cc = min i ol = 48ma ? 0.3 0.5 v v in = v ih or v il v h input hysteresis ? ? 200 ? mv i cc quiescent power supply current v cc = max., v in = gnd or v cc ? 0.01 1 ma dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v cc = 5.0v 5% notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. the test limit for this parameter is 5a at t a = ?55c. a 1 a 2 b 1 b 2 a 1 a 2 b 1 b 2 i = 2 i = 1 a 1 a 2 b 1 b 2 i = 0 dual 2-level single 4-level figure 1. data loading in 2-level operation note: 1. i = 3 for hold.
industrial temperature range 4 idt29fct520at/bt/ct multilevel pipeline register symbol parameter test conditions (1) min. typ. (2) max. unit ? i cc quiescent power supply current v cc = max. ? 0.5 2 ma ttl inputs high v in = 3.4v (3) i ccd dynamic power supply v cc = max. v in = v cc ? 0.15 0.25 ma/ current (4) outputs open v in = gnd mhz oe = gnd one input togging 50% duty cycle i c total power supply current (6) v cc = max. v in = v cc ? 1.5 3.5 ma outputs open v in = gnd f cp = 10mhz 50% duty cycle oe = gnd v in = 3.4v ? 2 5.5 one bit togging v in = gnd at fi = 5mhz 50% duty cycle v cc = max. v in = v cc ? 3.8 7.3 (5) outputs open v in = gnd f cp = 10mhz 50% duty cycle oe = gnd v in = 3.4v ? 6 16.3 (5) eight bits toggling v in = gnd at fi = 2.5mhz 50% duty cycle power supply characteristics notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + ? i cc d h n t + i ccd (f cp /2 + fini) i cc = quiescent current ? i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) fi = input frequency ni = number of inputs at fi all currents are in milliamps and all frequencies are in megahertz.
industrial temperature range idt29fct520at/bt/ct multilevel pipeline register 5 switching characteristics over operating range notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 29fct520at 29fct520bt 29fct520ct symbol parameter condition (1) min . (2) max. min . (2) max. min . (2) max. unit t phl propagation delay c l = 50pf 2 14 2 7.5 2 6 ns t plh clk to yx r l = 500 ? t phl propagation delay c l = 50pf 2 13 2 7.5 2 6 ns t plh s 0 or s 1 to yx t su set-up time, high or low 5 ? 2.5 ? 2.5 ? ns dx to clk t h hold time, high or low 2 ? 2 ? 2 ? ns dx to clk t su set-up time, high or low 5 ? 4 ? 4 ? ns i 0 or i 1 to clk t h hold time, high or low 2 ? 2 ? 2 ? ns i 0 or i 1 to clk t phz output disable time 1.5 12 1.5 7 1.5 6 ns t plz t pzh output enable time 1.5 15 1.5 7.5 1.5 6 ns t pzl t w clock pulse width high or low 7 ? 5.5 ? 5.5 ? ns
industrial temperature range 6 idt29fct520at/bt/ct multilevel pipeline register pulse generator r t d.u.t. v cc v in c l v out 50pf 500 ? 500 ? 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. octal link octal link octal link octal link octal link test circuits and waveforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width test switch open drain disable low closed enable low all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns.
industrial temperature range idt29fct520at/bt/ct multilevel pipeline register 7 ordering information so py q small outline ic shrink small outline package quarter-size small outline package 520at 520bt 520ct multilevel pipeline register xxxxx device type x package idt29fct corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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